幾何形狀對矽感應耦合電漿蝕刻的影響

反應離子蝕刻延遲（RIE-lag）是矽感應耦合電漿（ICP）蝕刻技術常發生的現象，影響製程均匀性，其發生尺寸範圍可達數百微米，愈小尺寸愈明顯。RIE-lag形成原因和幾何形狀與製程條件有密切關係，目前尚無有效解決方法的報導。本文研究設計不同幾何形狀尺寸圖案，包括等寬度，等長度，等面積的矩形或圓形，並控制製程氣體壓力，進行RIE-lag影響因素研究，得知幾何形狀中的寬度是影響RIE lag的主要因素，面積為次要因素；另外製程氣體壓力的改變，可改變RIE lag趨勢，在等面積圖案設計中，當壓力增加時，RIE lag現象可獲得改善，在適當壓力可以得到無反應離子蝕刻延遲（RIE lag-free）結果，且當壓力太高時，出現矽深蝕刻未被報導的反延遲（inverse RIE lag）結果，可知反應氣體對RIE lag影響中，C4F8保護氣體比SF6蝕刻氣體大。

The reactive ion etching (RIE) lag is a frequently seen defect affecting etching uniformity and appears in feature sizes up to hundreds of micrometers. The smaller feature size, the more obvius RIE lag. The RIE lag is relevant to the feature geometrical shape and process parameter. Different feature dimensions of rectangles, squares and circles/donuts are designed to realize how the geometrical shape affects RIE lag in inductively coupled plasma (ICP) etching process. Experimental results reveal that the primarily dominating factor in RIE lag is feature width and secondly factor is feature area as well as shape. Process parameters are also adjusted to control RIE lag magnitude and realize its mechanism. The inverse RIE lag phenomenon appears at much higher pressure of APC 75% which was not reported in Si deep etching so far as we know. It indicates that the cause of RIE lag in ICP etching is more attributed to the passivation gas than the etching gas during mass transport of reaction gases.