矽鍺漸變通道摻雜場效電晶體之研製

本論文主要是以矽鍺漸變（graded）層當作電洞傳導通道而開發之p型矽鍺場效電晶體結構，期藉由傳導通道中鍺含量之變化，進而提昇通道載子的侷限能力以及於通道內建構一反向內建電場，以抑制電導值於閘極順偏下急速下降，由實驗得知藉由通道中鍺含量的漸變結構，元件可以展示出比具有固定Ge含量之通道摻雜場效電晶體結構更高的電流密度，以及更大線性範圍操作下之電導值。

The experimental realization of a p-type Si/SiGe doped-channel field-effect transistor (DCFET), utilizing a strained and graded Si1-xGex well as the conducting channel, has been successfully fabricated. The graded variation of the Ge fraction in channel induced built-in field can prevent transconductance from shaping down drastically under forward gate bias and increase the carrier confinement for device operation. It is found that by grading Ge fraction in the channel, the devices exhibit the excellent property not only of higher current density but also enhancement in extrinsic transconductance and linear operation range over a wider dynamic range than those of devices with uniform Ge profile for the same integrated Ge dose in SiGe conducting well.