低光擾掃描電容顯微術在電性接面分析之應用

離子佈植後的熱處理是在矽基元件中形成電性接面的重要製程，掃描電容顯微術（scanning capacitance microscopy, SCM）雖早已被用於量測分析矽基元件中的電性接面，但其量測結果仍受到許多因素干擾而導致精確度降低。目前，在影響其精確度的幾項主要因素中，最近被發現的為光擾（photoperturbation）效應，也尚待解決之道。因試片基板區域的掃描面可提供試片製備的狀況、環境因素與光擾效應等重要訊息，透過基板區域的微分電容訊號可建立光擾之參考標準，進而作為電性接面分析之依據；此外，降低光擾效應可減少電性接面影像的量測誤差，再結合控制光擾強度的方法，即可探討不同熱處理製程對電性接面的影響，瞭解摻雜活化與點缺陷之間的微妙關係。本文將介紹決定光擾參考值的方法，並結合低光擾掃描電容顯微鏡技術與光擾控制探討熱處理製程對電性接面的影響。

Scanning capacitance microscopy (SCM) has been widely employed to map carrier distribution and electrical junctions. However, any photoperturbation may cause significant deterioration in the accuracy of the junction characterization. In this work, we demonstrated the method of controlling photoperturbation within SCM images and employed low-photoperturbed SCM to investigate the influence of annealing sequence on electrical junctions. Using low-photoperturbed SCM, operated under the same photoperturbation levels, we have observed the junction narrowing produced by post-spike furnace annealing (FA) at low temperatures. The experimental results indicate that the electrical junction formed by spike annealing is unstable.