微型自我時序微處理機－－基於FPGA的非同步電路設計實例

Tiny Self-timed Microprocessor: A Case Study of FPGA-based Asynchronous Circuit Design

油價不斷的攀升已不再是什麼值得訝異的新聞了，高價能源所延伸出的問題，在未來的幾年將日趨嚴重， 針對這問題尋找乾淨且便宜的替代能源當然是最好的解決辦法，然而我們並非能源方面的專才，因此我們將從其它的途徑，來為這個嚴重的總體問題盡一份心力。於過去幾年來我們致力於推廣低功耗的數位電路設計方法及從事相關EDA 工具的研究與開發，我們持續的將所有的研發能量投注於已被證實有低功耗特性的自我時序及非同步電路，已累積了多年來的研究成果與非同步電路實作經驗，我們在此提出一基於FPGA 的非同步數位系統設計流程，同時以一微型自我時序微處理機做為實際設計案例，並在Altera及Xilinx 的FPGA 實驗平臺上完成實體的測試驗證。該微處理機的非同步有限狀態機是採四相式延伸爆發模式協定所設計，自我時序資料流路徑則以資料包裹式協定搭配應對延遲元件所組成，在本文中將對該微型自我時序微處理機的結構、設計流程、高階合成、乃至FPGA 實作做更詳盡的說明，並同時以完成的模擬結果及實驗板上的量測數據來證明該基於FPGA 非同步數位系統設計流程的實用性。

In the past decades, academic and commercial asynchronous EDA tools are booming like bamboo shoots after a spring shower. However, the development of the tools is dispersed and lack of integration and compatibility. It is inconvenient for asynchronous circuit engineers and also for those who are potentially becoming one. In this paper, we present a practical asynchronous circuits design flow for rapid prototyping and design training. Collecting valuable findings and results from our past researches with National Science Council (NSC), a FPGAs-based asynchronous circuits design flow is revealed and confirmed with a complete sample design. A tiny RISC processor was implemented using the design flow and verified with both Altera and Xilinx FPGAs. The asynchronous controllers of the processor realized with four-phase extended burst-mode (XBM) machines. Push-mode bundled-data with matched delays is the basic technique for constructing the self-timed datapath. In the reset of this paper, the detailed design steps and related Verilog implementations are documented. The processor was not only verified by the comprehensive post place and route simulations but also the on-chip experiments and measurement.