具數位自動補償之次取樣鎖相迴路

Digitally Auto-Compensated Sub-Sampling PLL

本論文利用TSMC 90nm CMOS標準製程，完成具數位自動補償功能的次取樣鎖相迴路之電路設計與佈局。考量傳統鎖相迴路中的除頻器會造成充電幫浦平方倍的雜訊增益，本文採用次取樣鎖相迴路作為鎖定後的主要路徑，並針對其充電幫浦進行低功耗設計。同時，透過數位合成方式設計並實現自動補償電路，該電路能根據壓控振盪器當前的輸出頻段進行自動判斷與補償，確保輸出頻率精確達到目標值。在操作電壓為1.2V、參考頻率為75MHz、輸出頻率為2.4GHz的條件下，整體功率消耗為4.2mW，相位雜訊在1MHz偏移處為-110.2dBc，方均根抖動為1.76ps，晶片面積為0.81mm²，核心面積為0.0734mm²。
本論文首先探討鎖相迴路的基本架構與工作原理，並探討影響其性能的關鍵因素。接著，透過MATLAB Simulink進行電路行為模擬，再使用Hspice完成電路設計。在後續章節會介紹本論文所提出具數位自動補償之次取樣鎖相迴路設計，透過次取樣技術，在鎖定後消除除頻器造成的相位雜訊，並使用Cell-Based設計自動補償電路，使電路能在各狀況下正常運作。

This thesis presents the circuit design and layout of a sub-sampling phase-locked loop (PLL) with digital automatic compensation functionality, implemented using the TSMC 90 nm CMOS technology. To address the issue of squared noise gain caused by the divider in conventional PLLs, a Sub-Sampling PLL is employed as the primary path after locking. The charge pump is designed for low power consumption. Additionally, a digitally synthesized automatic compensation circuit is implemented, enabling real-time judgment and compensation based on the current output frequency band of the voltage-controlled oscillator (VCO), ensuring the output frequency precisely achieves the target value. In operating voltage of 1.2V, with a reference frequency of 75 MHz and an output frequency of 2.4 GHz, the circuit achieves a total power consumption of 4.2 mW. The phase noise at a 1 MHz offset is -110.2 dBc, the root mean square (RMS) jitter is 1.76 ps, the chip area is 0.81 mm², and the core area is 0.0734 mm².
Frist will exploring the fundamental architecture and working principles of PLLs, as well as the key factors affecting their performance. Circuit behavior simulations are conducted using MATLAB Simulink, followed by circuit design using Hspice. Subsequent chapters introduce the proposed sub-sampling PLL design with digital automatic compensation. By leveraging Sub-Sampling techniques, the design eliminates the phase noise induced by the divider after locking. Furthermore, the automatic compensation circuit, designed with a cell-based approach, ensures proper operation of the circuit under varying conditions