FPGA implementation of a lightweight simple encryption scheme to secure IoT using novel key scheduling technique

FPGA implementation of a lightweight simple encryption scheme to secure IoT using novel key scheduling technique

Internet of things (IoT), being the technology of this generation and several billions of electronic devices exchanging a huge secure information. With the low resource devices like the sensors, RFIDs etc. to the super computers and the clouds the security and privacy issues remain a concern. While the conventional cryptographic algorithms approved by the National Institute of Standards and Technology, could be embedded into the Low-resource devices their performance may be reduced, then the design of Ciphers for such resource constrained devices become a challenge with the security principles confidentiality, Integrity and Availability remains the same. This paper proposes, simple encryption schemes based on arithmetic operations Addition-Modulo/Multiplication Modulo, Rotation and XOR hence the name ARX/MRX. The cipher schemes have been implemented using reversible logic and Vedic Mathematics. The adders have been implanted using reversible logic and multipliers and the modular algorithms have been implemented using the combination of Vedic maths and Reversible logic. The software and hardware implementations are presented. The Histogram, Correlation coefficient and Entropy are found for the grayscale plaintext image using MATLAB to evaluate the security, and the hardware implementation is done writing Verilog code using Xilinx-Vivado and is verified using Nexys-4 Artix-7 FPGA the performance of the encryption schemes are analysed and compared with the existing literature.