Mean and variance statistic for image processing on FPGA

Mean and variance statistic for image processing on FPGA

Statistical formula processing an image data is commonly used in image processing. In software processing this formula and accessing data stored in memory is an easy task, but in hardware implementation, it is more difficult task due to many of constraints. This article presents hardware implementation of mean & variance statistic formula in effective and efficient way using FGPA Device. The design of circuit for both formulas proposed in this article need only two additions component (in two accumulators) and two shift-right-registers will be used for divisor circuits, one subtractor and one multiplier. In the experiment, processing an image size 8x8 pixels need 64 clocks cycle to conclude the mean & variance calculations. More than 1024 additions component is needed in some design so this design is more efficient.