應用灰色決策於伽瑪校正架構之硬體實作分析

在數位影像處理中普遍使用伽瑪校正(Gamma correction)來完成影像的增強(Enhancement)，以提升整體影像的品質。由於伽瑪校正含有除法及指數運算，軟體上實踐容易，但這些運算在硬體上不易實現。因此本研究藉由化簡的技術，將伽瑪校正的除法與指數運算化簡為硬體可實作之架構，以降低運算複雜度，並提升整體運算速度。此則並探討不同的硬體架構所產生的FPGA晶片邏輯數、延遲時間、執行頻率等。並使用Modelsim與Matlab模擬驗證硬體架構結果的正確性。最後並使用灰色系統的灰色決策來分析採用何種架構能完成晶片最佳性能之目標。

Gamma correction is commonly used in digital image processing for image enhancement to improve the quality of the images. Gamma correction can be provided using mathematical operations by division and exponent,, which is easy to practice on software it is nor easy to implement on hardware. In this paper, we implement the hardware architectures of division and exponent operations of Gamma correction by simplify technique. In addition, we study logic delay cell, dealy, and execution frequency of the FPGA chip on different hardware architecture. Then use Modelsim and Matlab to verify the correctness of the results of the hardware architecture. Finally we used grey decision making to decide what kind of hardware architecture can be getting the optimal performance.