改良式Jakes 衰減通道模擬器之硬體設計

The Design and Realization of the Improved Jakes Fading Channel Simulator

本文以原始Jakes模型為基礎，設計了一組硬體成本低廉，且容易實現的衰減通道模擬器，而低頻振盪器數目也比原來的模型要少許多。我們主要是把原始Jakes模型裡的路徑增益值採改良式分佈，而到達角度及起始角度都設為0度，這樣的設計不僅可以降低硬體成本，而且統計特性都比Zheng & Xiao模型更接近理想值。更明確的來說，改良式Jakes衰減通道模擬器只需要八個低頻振盪器，而此設計我們在Maxplus2的平台下用硬體描述語言來證實。經由Matlab模擬，我們得到ω（下標 n）的小數位數取7位元，弦波輸出值的小數位數取3位元，係數的小數位數取4位元即可。硬體實現時，memory bit數目只需512個，邏輯閘數目只需1,032個，而且模擬的結果證實此設計改良了原始模型的一階及二階的統計特性。

Based on the original Jakes model, we have proposed a new design for an inexpensive fading channel simulator that can be easily realized with many fewer low-frequency oscillators than used in existing structures. The major modifications from the original Jakes model include the generation of path gains under an improved distribution, and presetting the arrival angles and initial phases to be zero. These modifications not only reduce the hardware cost of the channel simulator, but also provide better statistic properties than the most recent model proposed by Zheng and Xiao. Specifically, the improved Jakes fading channel model presented in this paper needs only 8 low-frequency oscillators. The circuit design has been verified using hardware description language (HDL) over Maxplus2 software. The decimal precisions of the numerical presentations of the oscillating frequencies ω(subscript n), their cosine transformed values, and their coefficients are chosen as low as 7, 3, and 4 bits, respectively. Only 512 memory bits and1, 032 logic gates are needed in the circuit hardware. Simulation results have demonstrated that the proposed design exhibits improved first-order and second-order statistical properties.