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篇名
Implementation of CPLD-Based Quasi-Switched-Capacitor Step-Down DC-DC Converter
並列篇名
以CPLD為主之擬切換式電容降壓型直流轉換器的實作
作者 張原豪
中文摘要
A simple quasi-switched-capacitor (QSC) step-down DC-DC converter with multiple output choice (9V/5V, 9V/3.3V, 9V/2V) is designed and implemented via complex-programmable-logic-device-based (CPLD) digital controller for low-power applications (Input: 7.0~9.0V, load: 50~400Ohms). The integrated digital controller is implemented by combination with Verilog CPLD and ADC/DAC chips to achieve the closed-loop control of QSC converter. Such a Verilog-based CPLD can make controller design more flexible, simple and reliable. In fact, SC circuit needs no inductive element, so I.C. fabrication is promising, and it is pretty suitable for low-power VLSI applications. An interleaved current-mode control is employed here from battery source interleaved charging to the series capacitors of different cells by a voltage-controlled current source, so the continuous input current comes into being, and it results in a good feature: low electromagnetic interference (EMI). Such a current-mode control is able to not only enhance output robustness against source variation/noise, but also keep regulation capability of converter with loading variation. Finally, the hardware experiments are illustrated to show the efficacy of the scheme designed, including voltage conversion and output ripple, and output robustness against source variation.
起訖頁 455-472
關鍵詞 擬切換式電容降壓型直流轉換器硬體描述語言複合性可程式邏輯元件Quasi-switched-capacitorStep-downDC-DC converterVerilog-codeCPLD
刊名 朝陽學報  
期數 200809 (13期)
出版單位 朝陽科技大學
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