Wave Pipelined VLSI Architecture for a Viterbi Decoder Using Self Reset Logic with 0.65nm Technology

In 3G mobile terminals the Viterbi Decoder consumes approximately one third of the power consumption of a base band mobile transceiver. Viterbi decoders employed in digital wireless communications are complex and dissipate large power. A low power Viterbi decoder is designed in circuit level using self reset logic and wave pipelining technique is implemented for high speed operation. The Viterbi decoder consists of four units like branch metric unit, add compare and select unit and the survivor path memory unit. All these units are designed using the self reset logic and wave pipelining, and simulated with its layout using MICROWIND TOOL in the 0.65nm technology, 1.8V Vdd and at a frequency of 10GHz. The simulation result shows that the power consumption is reduced by 70.55% and the speed of the circuit is increased by 45.83% compared to the Single Rail Domino Logic for constraint length of K =3 to 7.